These years, semiconductor integrated circuits have achieved a higher level of integration, higher speed, and lower power consumption, and there has been an increasing demand for improving the quality of transistors. There are various methods of enhancing the ability of a transistor. Especially, a method of raising the mobility of carriers by applying a proper stress on a semiconductor device, with a stressed thin film layered on the surface thereof, is in widespread use because it is free from side effects, such as a capacity increase, in a transistor having a gate length of 100 nm or less (for example, refer to JP-A-2002-198368, JP-A-2005-57301, JP-A-2006-165335, and JP-A-2006-269768).
The conventional method of manufacturing a transistor using a stress applying film will be described with reference to the manufacturing processes in FIGS. 26 to 28.
As illustrated in FIG. 26(1), an element isolating region 114 of the STI (Shallow Trench Isolation) structure is formed on a silicon substrate 111.
Next, as illustrated in FIG. 26(2), a silicon oxide film (not illustrated) is formed through surface oxidation as a protective film for channeling prevention when the impurities are ion-implanted in the silicon substrate 111. Then, the impurities are ion-implanted respectively in the n-type transistor area and the p-type transistor area, thus forming a p-type well region 115 and a n-type well region 116.
Then, the protective silicon oxide film is removed and a gate oxide film 141 is newly formed in a thickness of about 1 to 3 nm as illustrated in FIG. 26(3).
Next, as illustrated in FIG. 26(4), after a polysilicon film is formed on the gate oxide film 141 with a film thickness of about 100 to 150 nm, a photolithography technique and a dry etching technique are used to form gate electrodes 143 and 163 with a polysilicon film.
Next, as illustrated in FIG. 27(5), through impurity implantation, n-type extension regions 131 and 132 are formed in the n-type transistor region through implantation of n-type impurities, such as As ions, P ions, and the like, while p-type extension regions 151 and 152 are formed in the p-type transistor region through implantation of p-type impurities, such as B ions and so on.
Next, as illustrated in FIG. 27(6), after gate side wall insulating films 133 and 153, including a silicon nitride film or oxide film with a thickness of about 20 nm to 50 nm, are formed according to the CVD method and the dry etching method, impurity ions are implanted, to form source/drain regions 135 and 136 in the n-type transistor region and source/drain regions 155 and 156 in the p-type transistor region. Then, by applying heat at a temperature of about 1050° C. instantaneously, the impurities are activated.
Next, as illustrated in FIG. 27(7), silicide electrodes 137, 138, 157, 158, 139, and 159 with thicknesses of about 20 nm to 50 nm are formed on the source/drain regions 135, 136, 155, and 156 and the gate electrodes 143 and 163 using cobalt (Co), nickel (Ni) or the like, according to salicide process technology, hence to reduce resistance there.
Next, as illustrated in FIG. 28(8), a compressive liner film 122 formed of a silicon nitride film having a compressive stress of about 1 GPa to 3 GPa, is formed on p-type transistor 103 in a thickness of about 20 nm to 60 nm according to the CVD method, optical lithography method, and dry etching method.
Further, as illustrated in FIG. 28(9), a tensile liner film 121 formed of a silicon nitride film having a tensile stress of about 1 GPa to 2 GPa, is formed on n-type transistor 102 through the CVD method, optical lithography method, and dry etching method. Due to the effect of this liner film, a compressive stress is applied to a channel of the p-type transistor in the direction of the channel to improve the mobility of holes and a tensile stress is applied to a channel of the n-type transistor to improve the mobility of electrons.
Next, as illustrated in FIG. 28(10), an interlayer insulating film 171 formed of silicon oxide (SiO2) or the like is formed through the CVD method. Further, after a contact hole is bored according to the dry etching technique, metal of tungsten (W) or the like is embedded to form contact electrodes 144, 145, 164, and 165 which connect to the source/drain regions 135, 136, 155, and 156, thereby a transistor 101 is completed.
In the conventional transistor structure, by forming a stressed thin film on the completed transistor device, it is possible to apply a stress on the device and improve the mobility of the transistor comparatively easily; however, there is a problem in that only a small stress is imposed on the channel of the transistor, compared with the stress of the thin film, because of the repulsive force from the gate electrodes. In order to impose a large stress there, it is necessary to get the film thicker or to get the internal stress itself of the film larger. When the film gets thicker, however, there are some problems, namely, it comes into contact with the adjacent transistor portion, which decreases the effect of stress, and boring a contact hole becomes difficult because a portion of the silicon nitride film becomes thicker. Further, when the internal stress of the film gets larger, there is a problem in that defects of the film, such as cracks, occur.
The problem to be solved is that, in the structure of forming a thin film having a stress on a transistor device, only a small stress can be applied on the channel of the transistor, compared with the stress of the thin film, because of the repulsive force from the gate electrodes.
The present invention aims to enhance a current increasing effect by increasing a stress to be applied on the transistor channel.